CLOCK DISTRIBUTION AND POWER MANAGEMENT / 16.5 16.5 Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS

Dynamic voltage scaling (DVS) has become a standard approach for reducing power when performance requirements vary. Voltage dithering was proposed to provide near-optimum DVS power savings with much less overhead [1]. Voltage dithering refers to operating for different fractions of time at two discrete voltage and frequency pairs to achieve an intermediate average frequency. Previous implementations apply voltage dithering to entire chips and require many microseconds to change operating voltage [1,2]. In this paper, a 90nm adder test chip that demonstrates the proposed concept of local voltage dithering (LVD) and couples LVD with sub-threshold operation to achieve ultra-dynamic voltage scaling (UDVS), is described.